1. Field of the Invention
The present invention relates to a switch and a method for organizing dataflow through a switch within packet switched or bursts switched networks. More particularly it relates to a switch within a telecommunication or data communication network, where the switch includes one or more outputs and a buffer unit, further it relates to a method for organizing dataflows in a telecommunication or data communication network including at least one switch where said switch is associated with at least one buffer.
2. Background Art
Despite the economic recession, network traffic continues to grow. Optical Packet Switching (OPS) is a promising candidate for a future cost effective network, supporting both high throughput and utilization. Two main issues of interest in OPS are however optical synchronization and buffering. Recently, a number of works have focused on using asynchronous packet switching, thereby avoiding the optical synchronization unit [1], [2]. (Bracketed references appear at the end of the specification.) Because of the immaturity of optical memory, Fiber Delay Line (FDL) based optical buffering in combination with using the wavelength dimension for contention resolution (i.e. a packet can be forwarded on an arbitrary wavelength leading to the destination), has been investigated [3], [2]. An alternative to FDL's is to use electronic memory with a limited number of buffer inputs [1,3]. In either case, buffer interfaces, consisting of FDL's or OE-converters (opto electronic converters), will represent a major cost factor for an optical packet switched system and should therefore be minimized [4].
Delay through an OPS network is negligible compared to transmission delay [1]. However, if the buffer has fewer input interfaces than the total number of switch inputs, only a fraction of the packets passing through the switch will be buffered and hence, delayed [1,4].
In an asynchronous system, if packets can be scheduled from the buffer to the outputs, without causing contention with new packets from the inputs, PLR (packet loss ratio) will be brought to a minimum limit. This approach is called In Input Priority (IP), since scheduling priority is given to the new packets arriving at the input, instead of to the buffered packets (i.e. Buffer Priority (BP)). In a Slotted IP system, this is simple. At the start of a time slot, packets in the buffer are scheduled only if there are vacant wavelengths after scheduling the packets arriving at the input. In asynchronous VLP (Variable Length Packets) operation, packet arrival and duration is not predictable. A new packet can arrive at the input at any random moment after a packet was scheduled from the buffer, hence making total Asynchronous IP (AIP) impossible when the number of buffer ports is limited.
Further, in asynchronous optical Metro packet rings, the same problem as above arises. When aggregating new packets onto the ring in the access nodes, packets already at the ring may contend with new packets. A detection circuit combined with a delay, e.g. a Fiber Delay Line (FDL), may be applied to first detect and then delay packets before passing the access node. However, this calls for extra components, both detectors and FDLs, making the principle potentially expensive. Additionally, in order to avoid packet collision when new packets enter the Metro ring, the FDLs will need to delay the packets longer than the duration of the longest of the new packets that enters the ring. This will impose additional delay of the packets already in the packet ring.
In this patent application, with reference to simulations, the ability of the fixed and incremental FDL buffering schemes described in [4], as well as electronic buffering, to support applications with a high demand to packet sequence and PLR is described.
Thus it is obvious that an asynchronous OPS system with a good PLR is needed. According to the present invention these and other problems will be solved using Asynchronous Input Priority.